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Ordering number : EN5997
CMOS IC
LC662508A, 662512A, 662516A
Four-Bit Single-Chip Microcontrollers with 8, 12, and 16 KB of On-Chip ROM
Overview
The LC662516A, LC662512A, and LC662508A are 4-bit CMOS microcontrollers that integrate on a single chip all the functions required in a special-purpose telephone controller, including ROM, RAM, I/O ports, a serial interface, a DTMF generator, timers, and interrupt functions. These microcontrollers are available in a 64-pin package.
*
Features and Functions
* On-chip ROM capacities of 8, 12, and 16 kilobytes, and an on-chip RAM capacity of 512 x 4 bits. * Fully supports the LC66000 Series common instruction set (128 instructions). * I/O ports: 58 pins * DTMF generator This microcontroller incorporates a circuit that can generate two sine wave outputs, DTMF output, or a melody output for software applications. * 8-bit serial interface: Two-wire interface (16-bit data length. Supports cascade connection.) * Instruction cycle time: 0.95 to 10 s (at 3.0 to 5.5 V) * Powerful timer functions and prescalers *
* * * * *
-- Time limit timer, event counter, pulse width measurement, and square wave output using a 12-bit timer. -- Time limit timer, event counter, PWM output, and square wave output using an 8-bit timer. -- Time base function using a 12-bit prescaler. Powerful interrupt system with 11 interrupt factors and 8 interrupt vector locations. -- External interrupts: 3 factors/3 vector locations -- Internal interrupts: 8 factors/5 vector locations (Waveform output internal interrupts: 3 factors and 1 vector; shared with external expansion interrupts) Flexible I/O functions Selectable options include 20mA drive outputs, inverter circuits, pull-up and open drain circuits. Optional runaway detection function (watchdog timer) 8-bit I/O functions Power saving functions using halt and hold modes. Packages: DIP64S, QIP64E (QFP64E) Evaluation ICs: LC665099 (evaluation chip) + EVA86K-ECB662500 LC66E2516(on-chip EPROM microcontroller)
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
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O1698RM (OT) No. 5997-1/17
LC662508A, 662512A, 662516A
Package Dimensions
unit: mm 3071-DIP64S
[LC662508A,12A,16A]
unit: mm 3159-QFP64E
[LC662508A,12A,16A]
SANYO: DIP64S
SANYO: QFP64E
Series Organization
Type No. LC66304A/306A/308A LC66404A/406A/408A LC66506B/508B/512B/516B LC66354A/356A/358A LC66354S/356S/358S LC66556A/558A/562A/566A LC66354B/356B/358B LC66556B/558B/562B/566B LC66354C/356C/358C LC662104A/06A/08A LC662304A/06A/08A/12A/16A LC662508A/12A/16A LC665304A/06A/08A/12A/16A LC66E308 LC66P308 LC66E408 LC66P408 LC66E516 LC66P516 LC66E2108 LC66E2316 LC66E2516 LC66E5316 LC66P2108 LC66P2316 LC66P2516 LC66P5316 No. of pins 42 42 64 42 42 64 42 64 42 30 42 64 48 42 42 42 42 64 64 30 42 64 52/48 30 42 64 48 ROM capacity 4 K/6 K/8 KB 4 K/6 K/8 KB 6 K/8 K/12 K/16 KB 4 K/6 K/8 KB 4 K/6 K/8 KB 6 K/8 K/12 K/16 KB 4 K/6 K/8 KB 6 K/8 K/12 K/16 KB 4 K/6 K/8 KB 4 K/6 K/8 KB RAM capacity 512 W 512 W 512 W 512 W 512 W 512 W 512 W 512 W 512 W 384 W DIP64S DIP42S DIP64S DIP42S DIP30SD DIP42S DIP64S DIP48S DIC42S with window DIP42S DIC42S with window DIP42S DIC64S with window DIP64S DIP42S DIP42S DIP64S DIP42S Package QFP48E QFP48E QFP64A QFP48E QFP44M QFP64E QFP48E QFP64E QFP48E MFP30S QFP48E QFP64E QFP48E QFC48 with window QFP48E QFC48 with window QFP48E QFC64 with window QFP64E Window and OTP evaluation versions 4.5 to 5.5 V/0.92 s Dual oscillator support 3.0 to 5.5 V/0.95 s On-chip DTMF generator versions 3.0 to 5.5 V/0.95 s Low-voltage versions 2.2 to 5.5 V/3.92 s Low-voltage high-speed versions 3.0 to 5.5 V/0.92 s 2.5 to 5.5 V/0.92 s Normal versions 4.0 to 6.0 V/0.92 s Features
4 K/6 K/8 K/12 K/16 KB 512 W 8 K/12 K/16 KB 512 W
4 K/6 K/8 K/12 K/16 KB 512 W EPROM 8 KB OTPROM 8 KB EPROM 8 KB OTPROM 8 KB EPROM 16 KB OTPROM 16 KB EPROM 8 KB EPROM 16 KB EPROM 16 KB EPROM 16 KB OTPROM 8 KB OTPROM 16 KB OTPROM 16 KB OTPROM 16 KB 512 W 512 W 512 W 512 W 512 W 512 W 384 W 512 W 512 W 512 W 384 W 512 W 512 W 512 W
DIC42S with window DIC64S with window DIC52S with window DIP30SD DIP42S DIP64S DIP48S
QFC48 with window QFC64 with window QFC48 with window MFP30S QFP48E QFP64E QFP48E
Window evaluation versions 4.5 to 5.5 V/0.92 s
OTP 4.0 to 5.5 V/0.95 s
No. 5997-2/17
LC662508A, 662512A, 662516A Pin Assignments DIP64S
QFP64E
Top view
We recommend the use of reflow-soldering techniques to solder-mount QFP packages. Please consult with your Sanyo representative for details on process conditions if the package itself is to be directly immersed in a dip-soldering bath (dip-soldering techniques).
No. 5997-3/17
LC662508A, 662512A, 662516A System Block Diagram
* When DT, ML, and DP are used, only the SIO channel can be used for serial I/O. * The INT3, INT4, and INT5 pins can be used with internal functions.
Differences between the LC665XX Series and the LC6625XX Series
Item System differences * Hardware wait time (number of cycles) when hold mode is cleared LC6650XB Series (Including the LC66599 evaluation chip) 65536 cycles About 64 ms at 4 MHz (Tcyc = 1 s) LC6655XB Series 16384 cycles About 16 ms at 4 MHz (Tcyc = 1 s) LC6625XX Series 16384 cycles About 16 ms at 4 MHz (Tcyc = 1 s)
* Value of timer 0 after a reset (Including the value after hold mode Set to FF0. is cleared) * DTMF generator * Inverter array * Three-value inputs/comparator inputs * Three-state output from P31 and P32 * Using P0 to clear halt mode * External extended interrupts None (Tools are handled with external devices.) None (Tools are handled with external devices.) Yes None In 4-bit groups For INT3, INT4, and INT5. (Tools are handled with external devices.) Shared with P90 (INT2) (Tools are handled with external devices.) * LC66506B/08B/12B/16B 4.0 to 6.0 V/0.92 to 10 s * LC66E516/P516 4.5 to 5.5 V/0.92 to 10 s P0, P1, P4, and P5: about 3 to 10 k * P2, P3, P6, P7, and PA: 15V handling * Others: Normal voltage
Set to FFC.
Set to FFC.
None None Yes None In 4-bit groups For INT3, INT4, and INT5.
Yes Yes None Yes Can be specified for each bit. INT3, INT4, and INT5 can be used with the internal functions.
* INT2 functions
Shared with P90 (INT2) * 3.0 to 5.5 V/0.92 to 10 s * LC6655XA, 56XA 2.2 to 5.5 V/3.92 to 10 s 3.0 to 5.5 V/1.96 to 10 s P0, P1, P4, and P5: about 3 to 10 k * P2, P3, P6, P7, and PA: 15V handling * Others: Normal voltage
Shared with P53 (INT2)
Differences in main characteristics * Operating power-supply voltage and operating speed (cycle time) * Pull-up resistors
3.0 to 5.5 V/0.95 to 10 s
P0, P1, P4, and P5: about 100 k P2, P3, P61, P63, and PA: 15V voltage handling Others: normal voltage
* Port voltage handling
No. 5997-4/17
LC662508A, 662512A, 662516A Pin Function Overview
Pin I/O Overview Output driver type Options State after a Standby mode reset operation Hold mode: Output off High or low (option) Halt mode: Output retained Hold mode: Output off High or low (option) Halt mode: Output retained
P00 P01 P02 P03
I/O
I/O ports P00 to P03 * Input or output in 4-bit or 1-bit units * P00 to P03 support the halt mode control function (This function can be specified in bit units.)
* Pch: Pull-up MOS type * Nch: Intermediate sink current type
* Pull-up MOS or Nch OD output * Output level on reset
P10 P11 P12 P13
I/O
I/O ports P10 to P13 Input or output in 4-bit or 1-bit units
* Pch: Pull-up MOS type * Nch: Intermediate sink current type
* Pull-up MOS or Nch OD output * Output level on reset
P20/SI0 P21/SO0 P22/SCK0 P23/INT0
I/O
I/O ports P20 to P23 * Input or output in 4-bit or 1-bit units * P20 is also used as the serial input SI0 pin. * P21 is also used as the serial output SO0 pin. * P22 is also used as the serial clock SCK0 pin. * P23 is also used as the INT0 interrupt request pin, and also as the timer 0 event counting and pulse width measurement input. I/O ports P30 to P32 * Input or output in 3-bit or 1-bit units * P30 is also used as the INT1 interrupt request. * P31 is also used for the square wave output from timer 0. * P32 is also used for the square wave and PWM output from timer 1. * P31 and P32 also support 3-state outputs.
* Pch: CMOS type * Nch: Intermediate sink current type * Nch: +15V handling when OD option selected
Hold mode: Output off CMOS or Nch OD output
H Halt mode: Output retained
P30/INT1 P31/POUT0 P32/POUT1
I/O
* Pch: CMOS type * Nch: Intermediate sink current type * Nch: +15V handling when OD option selected
Hold mode: Output off CMOS or Nch OD output H Halt mode: Output retained
P33/HOLD
I
Hold mode control input * Hold mode is set up by the HOLD instruction when HOLD is low. * In hold mode, the CPU is restarted by setting HOLD to the high level. * This pin can be used as input port P33 along with P30 to P32. * When the P33/HOLD pin is at the low level, the CPU will not be reset by a low level on the RES pin. Therefore, applications must not set P33/HOLD low when power is first applied.
P40/INV0I P41/INV0O P42/INV1I P43/INV1O
I/O
I/O ports P40 to P43 * Input or output in 4-bit or 1-bit units * Input or output in 8-bit units when used in conjunction with P50 to P53. * Can be used for output of 8-bit ROM data when used in conjunction with P50 to P53. * Dedicated inverter circuit (option)
* Pch: Pull-up MOS type * CMOS type when the inverter circuit option is selected * Nch: Intermediate sink current type
* Pull-up MOS or Nch OD output * Output level on reset * Inverter circuit
High or low or inverter I/O (option)
Hold mode: Port output off, inverter output off Halt mode: Port output retained, inverter output continues
Continued on next page.
No. 5997-5/17
LC662508A, 662512A, 662516A
Continued from preceding page.
Pin I/O Overview I/O ports P50 to P53 * Input or output in 4-bit or 1-bit units * Input or output in 8-bit units when used in conjunction with P40 to P43. * Can be used for output of 8-bit ROM data when used in conjunction with P40 to P43. * P53 is also used as the INT2 interrupt request. I/O ports P60 to P63 * Input or output in 4-bit or 1-bit units * P60 is also used as the SI1 serial input pin and as the ML melody output pin. * P61 is also used as the SO1 serial output pin. * P62 is also used as the SCK1 serial clock pin and the DT dial tone output pin. * P63 is also used for the event count input to timer 1. Output driver type Options State after a Standby mode reset operation
P50 P51 P52 P53/INT2
I/O
* Pch: Pull-up MOS type * Nch: Intermediate sink current type
* Pull-up MOS or Nch OD output * Output level on reset
Hold mode: Output off High or low (option) Halt mode: Output retained
P60/SI1/ML P61/S01/ P62/ SCK1/DT/ P63/PIN1
I/O
* Pch: CMOS type * Nch: Intermediate sink current type * Nch: +15V handling when OD option selected (P61 and P63 only)
CMOS or Nch OD output (When the ML or DT output is used, select open-drain output and provide an external pull-up resistor.)
Hold mode: Output off H Halt mode: Output retained
P70 P71 P72 P73
O
Output ports P70 to P73 * Output in either 1-bit or 4-bit units. * The contents of the output latch are input by input instruction.
* Pch: Pu MOS * Nch: Intermediate sink current type
Hold mode: Output off Pull-up MOS or Nch OD output H Halt mode: Output retained Hold mode: Output off High or low (option) Halt mode: Output retained Hold mode: Output off CMOS or Nch OD output H Halt mode: Output retained Hold mode: Output off Pull-up MOS or Nch OD output H Halt mode: Output retained Hold mode: Output off Pull-up MOS or Nch OD output H Halt mode: Output retained Hold mode: Port output off Inverter output off High or inverter I/O (option)
P80 P81 P82 P83
O
Output ports P80 to P83 * Output in either 1-bit or 4-bit units. * The contents of the output latch are input by input instruction.
* Pch: Pu MOS * Nch: Intermediate sink current type
* CMOS or Pch OD output * Output level on reset
P90 P91 P92 P93
I/O
I/O ports P90 to 93. * Input or output in either 1-bit or 4-bit units.
* Pch: CMOS * Nch: Intermediate sink current type
PA0 PA1 PA2 PA3
O
Output ports PA0 to PA3 * Output in either 1-bit or 4-bit units. * The contents of the output latch are input by input instruction.
* Pch: Pu MOS * Nch: +15-V handling when OD option selected
PB0 PB1 PB2 PB3
O
Output ports PB0 to PB3 * Output in either 1-bit or 4-bit units. * The contents of the output latch are input by input instruction.
* Pch: Pull-up MOS * Nch: Intermediate sink current type
PC0 PC1 PC2/INV2I PC3/INV2O
I/O
I/O ports PC0 to PC3 * Output in either 1-bit or 4-bit units. * Dedicated input ports PC2 to PC3 * Dedicated inverter circuits (option)
* Pch: CMOS * Nch: Intermediate sink current type
* CMOS or Nch OD output * Inverter circuit
Halt mode: Port output retained Inverter output retained
Continued on next page.
No. 5997-6/17
LC662508A, 662512A, 662516A
Continued from preceding page.
Pin I/O Overview Output driver type Options State after a Standby mode reset operation Inverter * Hold mode: output off * Halt mode: output continues Hold mode: input disabled Halt mode: input enabled Hold mode: Oscillator stops Halt mode: Oscillator continues
PD0/INV3I PD1/INV3O PD2/INV4I PD3/INV4O
I
Dedicated input ports PD0 to PD3 Dedicated inverter circuits (option)
* When the inverter circuit option is selected. * Pch: CMOS type * Nch: Intermediate sink current type
Inverter circuits
Normal input or inverter I/O (option)
PE0 PE1
I
Dedicated input ports
OSC1 OSC2
I O
System clock oscillator connections When an external clock is used, leave OSC2 open and connect the clock signal to OSC1. System reset input When the P33/HOLD pin is at the high level, a low level input to the RES pin will initialize the CPU. CPU test pin This pin must be connected to VSS during normal operation. Power supply pins
Ceramic oscillator or external clock selection
Option selection
RES
I
TEST
I
VDD VSS
Note: Pull-up MOS type: The output circuit includes a MOS transistor that pulls the pin up to VDD. CMOS output: Complementary output. OD output: Open-drain output
User Options 1. Ports 0, 1, 4, 5, and 8 output level at reset option The output levels at reset for I/O ports 0, 1, 4, 5, and 8 in independent 4-bit groups, can be selected from the following two options.
Option Output high at reset Output low at reset Conditions and notes The four bits of ports 0, 1, 4, 5, or 8 are set in a group The four bits of ports 0, 1, 4, 5, or 8 are set in a group
2. Oscillator circuit options * Main clock
Option Circuit Conditions and notes
External clock
OSC1
The input has Schmitt characteristics
C1
Ceramic oscillator Ceramic oscillator
OSC1
C2
OSC2
Note: There is no RC oscillator option.
No. 5997-7/17
LC662508A, 662512A, 662516A 3. Watchdog timer option A runaway detection function (watchdog timer) can be selected as an option. 4. Port output type options * The output type of each bit (pin) in ports P0, P1, P2, P3 (except for the P33/HOLD pin), P4, P5, P6, P7, P9, PA, PB, and PC can be selected individually from the following two options. (in1-bit units)
Option Circuit Output data Open-drain output Input data The ports P2, P3, P5, P6, and P9 inputs have Schmitt characteristics. P7, PA, and PB are output-only ports. Conditions and notes
DSB
Output data Output with built-in pull-up resistor
The ports P2, P3, P5, P6, and P9 inputs have Schmitt characteristics. The CMOS outputs (ports P2, P3, P6, P9, and PC) and the pull-up MOS outputs (P0, P1, P4, P5, P7, PA, and PB) are distinguished by the drive capacity of the p-channel transistor.
Input data
DSB
* The two options can be specified for P8 (in 1-bit units)
Option Circuit Conditions and notes
Open-drain output
Output data
Output data Output with built-in pull-up resistor (CMOS output)
No. 5997-8/17
LC662508A, 662512A, 662516A 5. Inverter array circuit option One of the following options can be selected for each of the following port sets: P40/P41, P42/P43, PC2/PC3, PD0/PD1, and PD2/PD3. (PDs do not use option 1 because they are dedicated to input.)
Option Circuit Output data Input data When the open-drain output type is selected Conditions and notes
DSB
Normal port I/O circuit Output data When the built-in pull-up resistor output type is selected. The CMOS outputs (PC) and the pull-up MOS outputs (P4) are distinguished by the drive capacity of the P-channel transistor.
Input data
DSB
Input Output data high Input data
DSB
Inverter I/O circuit Output Output data high Input data
If this option is selected, The I/O circuit is disabled by the DSB signal. Also note that the open-drain port output type option and the high level at reset option must be selected.
DSB
No. 5997-9/17
LC662508A, 662512A, 662516A LC662516 Series Option Data Area and Definitions
ROM area Bit 7 6 5 3FF0H 4 3 2 1 0 7 6 5 3FF1H 4 3 2 1 0 7 6 5 3FF2H 4 3 2 1 0 7 6 5 3FF3H 4 3 2 1 0 7 6 5 3FF4H 4 3 2 1 0 7 6 5 3FF5H 4 3 2 1 0 7 6 5 3FF6H 4 3 2 1 0 P5 P4 Unused Oscillator option P8 P1 P0 Watchdog timer option P13 P12 P11 P10 P03 P02 P01 P00 Unused P32 P31 P30 P23 P22 P21 P20 P53 P52 P51 P50 P43 P42 P41 P40 P73 P72 P71 P70 P63 P62 P61 P60 P93 P92 P91 P90 P83 P82 P81 P80 PB3 PB2 PB1 PB0 PA3 PA2 PA1 PA0 Output type 0 = OD, 1 = PU Output type 0 = OD, 1 = PU Output type 0 = OD, 1 = PU Output type 0 = OD, 1 = PU Output type 0 = OD, 1 = PU Output type 0 = OD, 1 = PU Output type 0 = OD, 1 = PU Output type 0 = OD, 1 = PU Output type 0 = OD, 1 = PU Output type 0 = OD, 1 = PU This bit must be set to 0. Output type 0 = OD, 1 = PU Output type 0 = OD, 1 = PU 0 = none, 1 = yes Output level at reset 0 = low level, 1 = high level Option specified Output level at reset Option/data relationship 0 = high level, 1 = low level This bit must be set to 0. 0 = external clock, 1 = ceramic oscillator
Continued on next page. No. 5997-10/17
LC662508A, 662512A, 662516A
Continued from preceding page.
ROM area Bit 7 6 5 3FF7H 4 3 2 1 0 7 6 5 3FF8H 4 3 2 1 0 7 6 5 3FF9H 4 3 2 1 0 7 6 5 3FFAH 4 3 2 1 0 7 6 5 3FFBH 4 3 2 1 0 7 6 5 3FFCH 4 3 2 1 0 7 6 5 3FFDH 4 3 2 1 0 Reserved. Must be set to predefined data values. This data is generated by the assembler. If the assembler is not used, set this data to 00. Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. Unused This bit must be set to 0. PC3 PC2 PC1 PC2 ML disabled option Unused Unused PD3 PD1 PC3 P43 P41 Inverter output 0 = inverter output, 1 = none 0 = disabled, 1 = enabled This bit must be set to 1. This bit must be set to 1. Output type 0 = OD, 1 = PU Unused This bit must be set to 0. Option specified Option/data relationship
Continued on next page. No. 5997-11/17
LC662508A, 662512A, 662516A
Continued from preceding page.
ROM area Bit 7 6 5 3FFEH 4 3 2 1 0 7 6 5 3FFFH 4 3 2 1 0 Reserved. Must be set to predefined data values. This data is generated by the assembler. If the assembler is not used, set this data to 00. Reserved. Must be set to predefined data values. This data is generated by the assembler. If the assembler is not used, set this data to 00. Option specified Option/data relationship
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Input voltage Symbol VDD max VIN1 VIN2 Output voltage VOUT1 VOUT2 ION1 ION2 Output current per pin -IOP1 -IOP2 -IOP3 ION1 Total pin current ION2 IOP1 IOP2 Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg VDD P2, P3 (except for the P33/HOLD pin), P61, and P63 All other inputs P2, P3 (except for the P33/HOLD pin), P61, P63, and PA All other inputs P0, P1, P2, P3 (except for the P33/HOLD pin), P4, P5, P6, P7, P8, P9, PA, PB, PC, PD1, PD3 P41, P43, PC3, PD1, PD3 P0, P1, P4, P5, P7, PA, PB P2, P3 (except for the P33/HOLD pin), P6, P8, P9, and PC P41, P43, PC3, PD1, PD3 P0, P1, P2, P3 (except for the P33/HOLD pin), PB, PC, and PD P4, P5, P6, P7, P8, P9, and PA P0, P1, P2, P3 (except for the P33/HOLD pin), PB, PC, and PD P4, P5, P6, P7, P8, P9, and PA Ta = -30 to +70C: DIP64S (QFP64E) Conditions Ratings -0.3 to +7.0 -0.3 to +15.0 -0.3 to VDD + 0.3 -0.3 to +15.0 -0.3 to VDD + 0.3 20 20 2 4 10 75 75 25 25 600 (430) -30 to +70 -55 to +125 Unit V V V V V mA mA mA mA mA mA mA mA mA mW C C 1 2 1 2 3 3 4 4 4 3 3 4 4 5 Note
Note: 1. Applies to pins with open-drain output specifications. For pins with other than open-drain output specifications, the ratings in the pin column for that pin apply. 2. For the oscillator input and output pins, levels up to the free-running oscillation level are allowed. 3. Sink current (Applies to P8 when the CMOS output specifications and applies to PD when the inverter array specifications are selected.) 4. Source current (Applies to all pins except P8 for which the pull-up output specifications, the CMOS output specifications, or the inverter array specifications have been selected. Applies to PD pins for which the inverter array specifications have been selected.) Contact your Sanyo representative for details on the electrical characteristics when the inverter array specifications option is selected. 5. We recommend the use of reflow soldering techniques to solder mount QFP packages. Please consult with your Sanyo representative for details on process conditions if the package itself is to be directly immersed in a dip-soldering bath (dip-soldering techniques).
No. 5997-12/17
LC662508A, 662512A, 662516A Allowable Operating Ranges at Ta = -30 to +70C, VSS = 0 V, VDD = 3.0 to 5.5 V, unless otherwise specified.
Parameter Operating supply voltage Memory retention supply voltage Symbol VDD VDDH VIH1 Input high-level voltage VIH2 VIH3 VIL1 Input low-level voltage VIL2 VIL3 Operating frequency (instruction cycle time) [External clock input conditions] OSC1: Defined by Figure 1. Input the clock signal to OSC1 and leave OSC2 open. (External clock input must be selected as the oscillator circuit option.) OSC1: Defined by Figure 1. Input the clock signal to OSC1 and leave OSC2 open. (External clock input must be selected as the oscillator circuit option.) OSC1: Defined by Figure 1. Input the clock signal to OSC1 and leave OSC2 open. (External clock input must be selected as the oscillator circuit option.) fop (Tcyc) VDD VDD: During hold mode P2, P3 (except for the P33/HOLD pin), P61, and P63: N-channel output transistor off P33/HOLD, P5, P60, P62, P9, RES, OSC1: N-channel output transistor off P0, P1, P4, P5, PC, PD, PE: N-channel output transistor off P2, P3 (except for the P33/HOLD pin), P5, P6, P9, RES, and OSC1: N-channel output transistor off P33/HOLD: VDD = 1.8 to 5.5 V P0, P1, P4, P5, PC, PD, PE, TEST: N-channel output transistor off Conditions min 3.0 1.8 0.8 VDD 0.8 VDD 0.8 VDD VSS VSS VSS 0.4 (10) typ max 5.5 5.5 13.5 VDD VDD 0.2 VDD 0.2 VDD 0.2 VDD 4.2 (0.95) Unit V V V V V V V V MHz (s) 3 1 2 3 2 Note
Frequency
fext
0.4
4.2
MHz
Pulse width
textH, textL
100
ns
Rise and fall times
textR, textF
30
ns
Note: 1. Applies to pins with open-drain specifications. However, VIH2 applies to the P33/HOLD pin. When ports P2, P3, and P6 have CMOS output specifications they cannot be used as input pins. 2. Applies to pins with open-drain specifications. P9 port pins with CMOS output specifications cannot be used as input pins. 3. PC port pins with CMOS output specifications cannot be used as input pins. Contact Sanyo for details on the allowable operating ranges for P4,PC, and PD pins with inverter array specifications.
No. 5997-13/17
LC662508A, 662512A, 662516A Electrical Characteristics at Ta = -30 to +70C, VSS = 0 V, VDD = 3.0 to 5.5 V unless otherwise specified.
Parameter Symbol IIH1 Conditions P2, P3 (except for the P33/HOLD pin), P61, and P63: VIN = 13.5 V, with the output Nch transistor off P0, P1, P4, P5, P6, P9, PC, TEST, RES, and P33/HOLD (Does not apply to P61 and P63.): VIN = VDD, with the output Nch transistor off PD, PE: VIN = VDD, with the output Nch transistor off Input ports other than PD and PE3: VIN = VSS, with the output Nch transistor off PD, PE: VIN = VSS, with the output Nch transistor off P2, P3 (except for the P33/HOLD pin), P6, P8, P9, and PC: IOH = -1 mA P2, P3 (except for the P33/HOLD pin), P6, P8, P9, and PC: IOH = -0.1 mA P0, P1, P4, P5, P7, PA, and PB P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, PA, PB, and PC (except for the P33/HOLD pin): IOL = 1.6 mA P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, PA, PB, and PC (except for the P33/HOLD pin): IOL = 8 mA P2, P3, P61, P63, and PA: VIN = 13.5 V Does not apply to P2, P3, P61, P63, P8, and PA: VIN = VDD P8: VIN = VSS -1.0 -1.0 -1.0 VDD - 1.0 V VDD - 0.5 30 100 300 0.4 1.5 5.0 1.0 k V V A A A 5 5 6 6 7 3 min typ max 5.0 Unit A Note 1
Input high-level current
IIH2
1.0
A
1
IIH3 IIL1 Input low-level current IIL2
1.0
A A A
1 2 2
Output high-level voltage
VOH1
Value of the output pull-up resistor
RPO VOL1
Output low-level voltage VOL2 IOFF1 Output off leakage current IOFF2 IOFF3 [Schmitt characteristics] Hysteresis voltage High-level threshold voltage Low-level threshold voltage [Ceramic oscillator] Oscillator frequency Oscillator stabilization time [Serial clock] Cycle time Input Output tCKCY tCKL tCKH tCKR, tCKF fCF fCFS VHYS Vt H Vt L
0.1 VDD P2, P3, P5, P6, P61, P9, RES, OSC1 (EXT) 0.5 VDD 0.2 VDD OSC1, OSC2: See Figure 2. 4 MHz See Figure 3. 4 MHz 4.0 10.0 0.8 VDD 0.5 VDD
V V V
MHz ms
0.9 2.0 SCK0, SCK1: With the timing of Figure 4 and the test load of Figure 5. 0.4 1.0 0.1
s Tcyc s Tcyc s
Low-level and high-level Input pulse widths Output Rise an fall times [Serial input] Data setup time Data hold time [Serial output] Output delay time Output
tICK tCKI
SI0, SI1: With the timing of Figure 4. Stipulated with respect to the rising edge () of SCK0, SCK1.
0.3 0.3
s s
tCKO
SO0, SO1: With the timing of Figure 5 and the test load of Figure 5. Stipulated with respect to the falling edge () of SCK0, SCK1.
0.3
s
Continued on next page.
No. 5997-14/17
LC662508A, 662512A, 662516A
Continued from preceding page.
Parameter [Pulse conditions] INT0 high and low-level pulse widths High and low-level pulse widths for interrupt inputs other than INT0 PIN1 high and low-level pulse widths RES high and low-level pulse widths INT0: Figure 6, conditions under which the INT0 interrupt can be accepted, conditions under which the timer 0 event counter or pulse width measurement input can be accepted INT1, INT2: Figure 6, conditions under which the corresponding interrupt can be accepted PIN1: Figure 6, conditions under which the timer 1 event counter input can be accepted RES: Figure 6, conditions under which reset can be applied. Symbol Conditions min typ max Unit Note
tIOH, tIOL
2
Tcyc
tIIH, tIIL tPINH, tPINL tRSH, tRSL
2 2 3
Tcyc Tcyc Tcyc
Operating current drain
IDD OP IDDHALT IDDHOLD
VDD: 4MHz ceramic oscillator VDD: 4MHz external clock VDD: 4MHz ceramic oscillator VDD: 4MHz external clock VDD: VDD = 1.8 to 5.5 V
4.5 4.5 2.5 2.5 0.01
8.0 8.0 5.5 5.5 10
mA mA mA mA A
8
Halt mode current drain Hold mode current drain
Note: 1. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. These pins cannot be used as input pins if the CMOS output specifications are selected. 2. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. The rating for the pull-up output specification pins is stipulated in terms of the output pull-up current IPO. These pins cannot be used as input pins if the CMOS output specifications are selected. 3. With the output Nch transistor off for CMOS output specification pins. (Also applicable when the p-channel open-drain option is specified for P8.) 4. With the output Nch transistor off for pull-up output specification pins. 5. Applies to P8 when the CMOS output specifications are selected. 6. With the output Nch transistor off for open-drain output specification pins. 7. With the output Pch transistor off for open-drain output specification pins. 8. Reset state
Tone (DTMF) Output Characteristics DC Characteristics at Ta = -30 to +70C, VSS = 0 V 1. When the MLOUT enable option is selected (the ML output function can be used)
Parameter Tone output voltage (p-p) Row/column tone output voltage ratio Tone distortion Symbol VT1 DBCR1 THD1 Conditions DT: Dual tone, VDD = 3.5 to 5.5 V* DT: Dual tone, VDD = 3.5 to 5.5 V* DT: Single tone, VDD = 3.5 to 5.5 V* min 0.9 1.0 typ 1.3 2.0 2 max 2.0 3.0 7 Unit V dB %
Note: * See item 2. below if the MLOUT disable mask option is selected.
2. When the MLOUT disable option is selected (the ML output function cannot be used)
Parameter Tone output voltage (p-p) Row/column tone output voltage ratio Tone distortion Symbol VT1 DBCR1 THD1 Conditions DT: Dual tone, VDD = 3.0 to 5.5 V* DT: Dual tone, VDD = 3.0 to 5.5 V* DT: Single tone, VDD = 3.0 to 5.5 V* min 0.9 1.0 typ 1.3 2.0 2 max 2.0 3.0 7 Unit V dB %
Note: * See item 1. above if the MLOUT enable mask option is selected.
No. 5997-15/17
LC662508A, 662512A, 662516A
VDD 0.8 VDD 0.2 VDD VSS
External clock
OSC1
(OSC2) Open textF textL textR 1/fext textH
Figure 1 External Clock Input Waveform
OSC1
OSC2
Operating VDD lower limit
C1
Ceramic oscillator
C2
Stable oscillation Oscillator unstable period tCFS
Figure 2 Ceramic Oscillator Circuit
Figure 3 Oscillator Stabilization Period
Table 1 Recommended Ceramic Oscillator Constants
External capacitor type 4 MHz (Murata Mfg. Co., Ltd.) CSA4.00MG 4 MHz (Kyocera Corporation) KBR4.0MSB C1 = 33 pF C2 = 33 pF C1 = 33 pF C2 = 33 pF Built-in capacitor type 4 MHz (Murata Mfg. Co., Ltd.) CST4.00MG 4 MHz (Kyocera Corporation) KBR4.0MKC
tCKCY SCK0 SCK1 0.2 VDD (output) 0.4 VDD (intput) SI0 SI1 tCK0 SO0 SO1 VDD - 1 0.4 VDD tCKL tCKR tCKH tCKF 0.8V DD (input) VDD - 1 (output) tICK tCKI 0.8 VDD 0.2 VDD Test point
R = 1k C = 50 pF
Figure 4 Serial I/O Timing
Figure 5 Timing Load
No. 5997-16/17
LC662508A, 662512A, 662516A
tI0H tI1H tPINH tRSH 0.8 VDD 0.2 VDD tI0L tI1L tPINL tRSL
Figure 6 Input Timing for the INT0, INT1, INT2, PIN1, and RES pins
Figure 7 Tone Output Pin Load
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of October, 1998. Specifications and information herein are subject to change without notice. PS No. 5997-17/17

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